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Title:  Sr. or Staff Signal Integrity Engineer

Company:  Renesas Semiconductor Design (Beijing) Co., Ltd.
Country/Region:  CN
City:  shanghai
Business Unit:  IoT and Infrastructure Business Unit
Office:  CN, Shanghai (RESH)
Job Function:  Hardware (Digital)
Job Type: 


  • Work with a cutting edge DDR4/5 product design team to simulate, analyze and improve the signal integrity and power integrity performance of chip, package and board.
  • Align and trade off the SI/PI design target with cross function team. Support the package, IO buffer and die/package PDN design. Review the SI/PI performance of the die and package design,
  • Create simulation bench to perform pre-layout and post-layout simulation of signal integrity and power integrity.
  • Extract the S parameter/RLC/TLine model, according to specific accuracy, bandwidth and simulation time requirement.
  • Lab measurement to verify the SI/PI performance and trouble shooting.


  • Minimum BSEE, MSEE preferred;
  • 3+ yrs. of experience on signal integrity area;
  • Strong knowledge of transmission line theory and electromagnetic field theory, such as reflection, crosstalk, SSN and power noise.
  • Experience in signal integrity simulation and analysis on DDR or other multi-loading system is required
  • Knowledge of semiconductor package and circuit design. Good understanding of IO buffer architecture and IO analog design is a very strong plus.
  • Knowledge of chip/package PDN design.
  • Experience in 2D/2.5D/3D model extraction tool, HFSS and Cadence/Sigrity tool is a plus
  • Experience in circuit simulator, ADS/Hspice/Spectra is a plus