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タイトル:  Validation Engineer

会社名:  Renesas Semiconductor Design (Beijing) Co., Ltd.
国/地域:  CN
部署:  Solution Development Department
場所: 

CN

職務機能:  Validation Engineer

Responsibility

- Take charge of verification for Vcore product.

- Responsible for make verification plan according to protocol and IC specification

- Develop verification environment and verification items according to verification plan

- Carried out verification and debug

- Make relevant technical documents

 

Qualification:

- Bachelor degree or above in EE or related field

- 2+ years of experiences on design/verification area.

- Familiar with digital simulations and related EDA tools

- Proficient in Verilog / SystemVerilog

- Familiar with UVM and AMS verification is preferred

- Familiar with PMIC and IIC interface is preferred

-       Highly organized and self-motivated, and working well with teammates