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Title:  Staff ASIC Digital Design Engineer

Company:  Renesas Electronics America Inc.
Country/Region:  US
State:  AZ
City:  Tempe
Department: 
Business Unit:  IoT and Infrastructure Business Unit
Office:  Tempe
Job Function:  Hardware (Digital)
Job Type:  Permanent
Description: 

Renesas Electronics Americas (REA) is a dynamic, multi-cultural tech company where employees can learn, mentor and thrive. REA brings together the strong financial foundation of a multi-billion dollar global operation and the flexibility and velocity of a smaller organization. We are developing technologies for the latest advances in mobile computing, secured connected devices, autonomous driving, smart homes and factories and more. Our solutions are at the heart of products developed by the major innovators around the world. Join us and be part of what’s next in electronics.

 

To further strengthen the team at our Tempe location we are looking for a Staff ASIC Digital Design Engineer who will work on the development of state of the art mixed-signal PLL (phase-locked loop) integrated circuits. The Staff ASIC Design Engineer will work on the development of the integrated circuits by doing design specification and RTL coding, front-end implementation and STA, verification, FPGA validation, prototype testing on the bench, etc. This will all be done in close collaboration with the analog, digital, implementation and verification engineers, as well the system architects and marketers.

 

Basic Qualifications:

The ideal candidate will have the following attributes:

  • Experience with architecting digital designs and writing device-level or sub-system specifications
  • Experience with Verilog and/or SystemVerilog for digital design and verification
  • Experience in digital design implementation including logical synthesis and DFT insertion with high coverage
  • Experience in static timing analysis and creation of place and route constraints
  • Experience in formal verification, lint and CDC checking
  • Experience in asynchronous clock crossings and synthesis implications of RTL
  • Experience in implementing and verifying ECOs on RTL, synthesized, and post route netlists
  • Experience with gate-level simulations, causes and implications of timing violations
  • Experience in ATPG and ATE support
  • Fast learner with ability to work under minimal supervision
  • Strong organization and communication skills

 

Preferred Skills & Knowledge

  • Knowledge of timing and synchronization standards is a strong asset
  • Experience with mixed signal circuits is an asset
  • SOC design experience is an asset
  • Experience with scripting in Tcl, Perl, Python, bash, etc.

 

Education and/or Experience

  • Electrical or Computer Engineering degree and 8+ years of practical experience. 

 

Equal Opportunity Employer: Disability/Veteran


Nearest Major Market: Phoenix