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Title:  Analog and Mixed-Signal Design Engineer


Tempe, US

Job Function:  Hardware(Analog)

Renesas is a global semiconductor company providing hardware and software solutions for a range of cutting-edge technologies including self-driving cars, robots, automated factory equipment, and smart home applications. We are a key supplier to the world’s leading manufacturers of the electronics you rely on every day; you may not see our products, but they are all around you.


Renesas is a global, multi-billion dollar, publicly-traded company headquartered in Japan, and has subsidiaries in 20 countries worldwide. Renesas is a dynamic, multi-cultural technology company where employees learn, mentor, innovate and thrive. Renesas is extending our share in fast-growing data economy-related markets such as infrastructure and data center, and strengthening our presence in the industrial/IOT and automotive segments. Our solutions drive products developed by major innovators around the world. Join us and build your future by being part of what’s next in electronics.

Location: Tempe, AZ


Job Description:

Perform design, simulation, and layout of industry-leading high performance timing products - PLL circuits with low-jitter, fractional-N synthesizers utilizing sigma-delta concepts, and low phase noise VCO designs.  Translate technical and performance requirements into design specifications; perform modeling of circuits at various levels, optimize circuit designs in order to achieve very low noise and high performance; run simulations using EDA tools to verify designs; perform block and top-level layout and guide layout engineers.


Position Requirements:

  • A PhD or MSEE with 5 years professional IC design experience
  • Education or experience must include an understanding of transistor level design, block level integration, and block level simulation
  • Must be familiar with simulation tools in order to efficiently simulate analog and mixed-signal circuits
  • Knowledge of integer PLLs, fractional-N synthesizers, and VCO design is a plus
  • Knowledge of verilog and systemVerilog and the ability to write behavioral models for complex circuit blocks is also a plus


Equal Opportunity Employer: Disability/Veteran


Nearest Major Market: Phoenix