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Title:  Staff Validation Engineer

Company:  Integrated Device Technology, Inc.
Country/Region:  CN
State: 
City:  Shanghai
Department: 
Business Unit:  IoT and Infrastructure Business Unit
Office:  IDT(Shanghai)
Job Function:  Production and Technology
Job Type:  Permanent
Description: 

<span style="font-family:"Arial",sans-serif">Staff Validation Engineer

<span style="font-family:"Arial",sans-serif">Location: Shanghai, China

 

<span style="font-family:"Arial",sans-serif">Responsibilities:

  • <span style="font-family:"Arial",sans-serif">Work with other teams such as design, product definition, application to develop test plans for reaching targeted coverage and ensure the quality of the product.
  • <span style="font-family:"Arial",sans-serif"><span style="font-family:"Arial",sans-serif">Work with design and/or verification teams to generate the test patterns to support the test plan.
  • <span style="font-family:"Arial",sans-serif"><span style="font-family:"Arial",sans-serif">Develop necessary C++ test methods and associated testflow necessary to perform validation of specification parameters.
  • <span style="font-family:"Arial",sans-serif"><span style="font-family:"Arial",sans-serif">Maintain revision control of test program development and final release.
  • <span style="font-family:"Arial",sans-serif"><span style="font-family:"Arial",sans-serif">Track test program versions with each respective product.
    <span style="font-family:"Arial",sans-serif"> 

<span style="font-family:"Arial",sans-serif">Requirements:

  • <span style="font-family:"Arial",sans-serif">Power user of 93k tester, especially PS9G card.
  • <span style="font-family:"Arial",sans-serif"><span style="font-family:"Arial",sans-serif">Extensive knowledge of pin electronics, multiport timing, equation-based timing, signal termination.
  • <span style="font-family:"Arial",sans-serif"><span style="font-family:"Arial",sans-serif">Prior experience of operating ATE with data rate range in 1 to 10 Gpbs
  • <span style="font-family:"Arial",sans-serif"><span style="font-family:"Arial",sans-serif">Hand-on experience of converting evcd files to ATE patterns
  • <span style="font-family:"Arial",sans-serif"><span style="font-family:"Arial",sans-serif">Fluent in C++ to implement test methods.
  • <span style="font-family:"Arial",sans-serif"><span style="font-family:"Arial",sans-serif">Familiar with revision control tool and concept.
  • <span style="font-family:"Arial",sans-serif"><span style="font-family:"Arial",sans-serif">Basic understand of IC design
  • <span style="font-family:"Arial",sans-serif"><span style="font-family:"Arial",sans-serif">Minimum <span style="font-family:"Arial",sans-serif">6<span style="font-family:"Arial",sans-serif"> year industrial experience in ATE based validation work.
  • <span style="font-family:"Arial",sans-serif"><span style="font-family:"Arial",sans-serif">BSEE or MSEE is required.