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Title:  Staff Signal Integrity Engineer

Company:  Integrated Device Technology, Inc.
Country/Region:  CN
City:  Shanghai
Business Unit:  IoT and Infrastructure Business Unit
Office:  IDT(Shanghai)
Job Function:  Hardware (Digital)
Job Type:  Permanent

Position: Staff/ Principal Signal Integrity Engineer

Location: Shanghai, China


About IDT, a Renesas Electronics Company

Teamwork, innovation and impact are the root of our corporate culture. IDT/Renesas is seeking individuals who want to maximize their impact on our technology, our customers and company. We recognize that our talented workforce makes us a top performer in our industry. We foster a positive and collaborative environment where ideas are shared and nurtured.


IDT/Renesas is a dynamic, multi-cultural tech company where employees can learn, mentor and thrive. IDT/Renesas brings together the strong financial foundation of a multi-billion dollar global operation and the flexibility and velocity of a smaller organization. We are developing technologies for the latest advances in mobile computing, secured connected devices, autonomous driving, smart homes and factories and more. Our solutions are at the heart of products developed by the major innovators around the world. Join us and be part of what’s next in electronics.


Our offer

With one of our top priorities being to attract, retain and develop our world-class workforce, your career or internship at IDT/Renesas is guaranteed to be challenging, stimulating and rewarding - both personally and professionally. We give you the tools, support and resources to put great ideas together into successful products. 




  • Work with a cutting edge DDR4/5 product design team to simulate, analyze and improve the signal integrity and power integrity performance of chip, package and board.

  • Align and trade off the SI/PI design target with cross function team. Support the package, IO buffer and die/package PDN design. Review the SI/PI performance of the die and package design,

  • Create simulation bench to perform pre-layout and post-layout simulation of signal integrity and power integrity.

  • Extract the S parameter/RLC/TLine model, according to specific accuracy, bandwidth and simulation time requirement.

  • Lab measurement to verify the SI/PI performance and trouble shooting.



  • Minimum BSEE, MSEE preferred;

  • 6+ yrs. of experience on signal integrity area;

  • Strong knowledge of transmission line theory and electromagnetic field theory, such as reflection, crosstalk, SSN and power noise.

  • Experience in signal integrity simulation and analysis on DDR or other multi-loading system is required

  • Knowledge of semiconductor package and circuit design. Good understanding of IO buffer architecture and IO analog design is a very strong plus.

  • Knowledge of chip/package PDN design.

  • Experience in 2D/2.5D/3D model extraction tool, HFSS and Cadence/Sigrity tool is a plus

  • Experience in circuit simulator, ADS/Hspice/Spectra is a plus


IDT/Renesas is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment regardless of race, color, religion, sex, national origin, disability, protected veteran status, or any other characteristic protected by law.