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Title:  Staff Verification Engineer

Company:  Integrated Device Technology, Inc.
Country/Region:  CN
City:  Shanghai
Business Unit:  IoT and Infrastructure Business Unit
Office:  IDT
Job Function:  Hardware (Digital)
Job Type:  Permanent

Position: Staff Verification Engineer

Location: Shanghai, China


About IDT, a Renesas Electronics Company

Teamwork, innovation and impact are the root of our corporate culture. IDT/Renesas is seeking individuals who want to maximize their impact on our technology, our customers and company. We recognize that our talented workforce makes us a top performer in our industry. We foster a positive and collaborative environment where ideas are shared and nurtured.


IDT/Renesas is a dynamic, multi-cultural tech company where employees can learn, mentor and thrive. IDT/Renesas brings together the strong financial foundation of a multi-billion dollar global operation and the flexibility and velocity of a smaller organization. We are developing technologies for the latest advances in mobile computing, secured connected devices, autonomous driving, smart homes and factories and more. Our solutions are at the heart of products developed by the major innovators around the world. Join us and be part of what’s next in electronics.


Our offer

With one of our top priorities being to attract, retain and develop our world-class workforce, your career or internship at IDT/Renesas is guaranteed to be challenging, stimulating and rewarding - both personally and professionally. We give you the tools, support and resources to put great ideas together into successful products. 



  • Understanding the expected functionality of designs.
  • Developing testing and regression plans.
  • Designing and developing verification environment.
  • Running RTL, gate-level and AMS simulations/regression.
  • Code/functional coverage development, analysis and closure.



  • MS in EE/CS/ME.
  • Minimum of 7 years’ experience.
  • Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
  • Candidate should be familiar with as System Verilog, UVM verification methodology.
  • Candidate should be familiar with industry standard ASIC design and verification tools and flow.
  • Good knowledge ddr protocol and computer system architecture would be an added advantage.
  • Good knowledge of Perl and shell programming would be an added advantage.
  • Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
  • Knowledge in ASIC/FPGA design process and verification tools.
  • Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
  • Scripting and automation skills (tcl, perl, makefile etc) a plus.
  • Familiar with C/C++.
  • Knowledge of DDR protocol a plus.
  • Independent and self-managing.


IDT/Renesas is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment regardless of race, color, religion, sex, national origin, disability, protected veteran status, or any other characteristic protected by law.