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Title:  Test Engineering Manager

Company:  Renesas Electronics America Inc.
Country/Region:  US
State:  CA
City:  San Jose
Business Unit:  IoT and Infrastructure Business Unit
Office:  US, San Jose (REA)
Job Function:  Hardware(Analog)
Job Type:  Permanent

Renesas Electronics Americas (REA) is a dynamic, multi-cultural tech company where employees can learn, mentor and thrive. REA brings together the strong financial foundation of a multi-billion dollar global operation and the flexibility and velocity of a smaller organization. We are developing technologies for the latest advances in mobile computing, secured connected devices, autonomous driving, smart homes and factories and more. Our solutions are at the heart of products developed by the major innovators around the world. Join us and be part of what’s next in electronics.


Test development engineers are critical to Renesas/IDT's Wireless Power Division (WPD).  They interface directly with the design team to define unique and novel test modes for our current and future generation products.  Test engineers also play a critical role in working with the applications team to shape the final device datasheet through characterization and DFT activities. 


As a test engineer, you are involved with the entire NPI (new production introduction) process that starts from feasibility, DFT, test H/W design, device bring up, ATE characterization, all the way to offshore production test program release. It is test engineer’s job to ensure that each device shipped meets the REA’s high quality standards. At the same time, a test engineer also works constantly to identify areas to maximize efficiency, test yield and minimize test cost.


Minimum Requirements:

  • Bachelor’s degree in electrical/computer engineering or computer science
  • 8+ years of experience test H/W and test program development
  • Strong test development and debug skills on Advantest SOC test platform – PS1600. Experience on Teradyne MicroFlex is a plus.
  • Hands-on experience on ATE test development for analog and mixed signal devices. Proficient with ATE analog instruments, strong debug/troubleshooting experience
  • Strong experience in vectors generation and conversion
  • Familiar with vector generation tools such as VTRAN/Velocity, and ability to write vector generation tools
  • Strong experience in programming in such as C/C++, Perl, python, etc.


Preferred Requirements:

  • Familiar with high speed ASIC/SOC devices
  • Master’s degree in electrical/computer engineering or computer science
  • Experience in ATE characterization
  • Familiar with trimming and OTP for deep sub-micron devices in production test
  • Experience with memory test algorithms
  • Experience with serial interfaces such as JTAG, SMbus, and SPI


Equal Opportunity Employer: Disability/Veteran

Nearest Major Market: San Jose
Nearest Secondary Market: Palo Alto