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Title:  Staff Packaging Engineer

Company:  Renesas Electronics America Inc.
Country/Region:  US
State:  CA
City:  San Jose
Department: 
Business Unit:  Production and Technology Unit
Office:  REA(San Jose)
Job Function:  Production and Technology
Job Type:  Permanent
Description: 

Renesas is a global semiconductor company providing hardware and software solutions for a range of cutting-edge technologies including self-driving cars, robots, automated factory equipment, and smart home applications. We are a key supplier to the world’s leading manufacturers of the electronics you rely on every day; you may not see our products, but they are all around you.

 

Renesas is a global, multi-billion dollar, publicly-traded company headquartered in Japan, and has subsidiaries in 20 countries worldwide. Renesas is a dynamic, multi-cultural technology company where employees learn, mentor, innovate and thrive. Renesas is extending our share in fast-growing data economy-related markets such as infrastructure and data center, and strengthening our presence in the industrial/IOT and automotive segments. Our solutions drive products developed by major innovators around the world. Join us and build your future by being part of what’s next in electronics.

 

Responsibilities:

  • Design and optimize complex wire bond and flip chip packages, modules and sub-systems for excellent RF, signal and power integrity performance.
  • Work with IC and system design teams in an IC-Package-PCB co-design setting to help floor-plan the chip padding and PCB pinout that facilitates optimized package and module layout.
  • Able to take a package from concept to mass production. That includes package selection, layout, modeling, simulations, optimizations, RFQ and manufacturing risk assessment. Ensure design for manufacturability and meet cost constraints.
  • Build models for packages, boards, connectors, vias, interconnects and other components needed for end-to-end design and signal integrity optimization for serial and parallel interfaces.
  • Expertise at optimizing packages and systems for thermal and thermo-mechanical performance a plus.
  • Work with customers to debug design and performance issues where and when necessary.
  • Develop methodologies and processes to improve SI and PI modeling approaches. Drive towards automation to improve performance and efficiency.

 

Requirements:

  • MSEE required with 6+ years of IC package design and layout, signal integrity modeling and simulation experience.
  • Solid background in Electromagnetics & High Speed Design theory. RF design experience a plus.
  • Able to whip out tools like HFSS, SI-Wave, Q3D, ADS, Hspice, Ansys, Flotherm and solve the problem at hand.
  • Working level knowledge of package and PCB design tools like Cadence Allegro package and PCB designer.
  • Knowledge of assembly and substrate manufacturing processes a big plus.

 

Equal Opportunity Employer: Disability/Veteran

 


Nearest Major Market: San Jose
Nearest Secondary Market: Palo Alto