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Title:  Senior Staff ASIC Digital Design Engineer


Ottawa, CA

Job Function:  Hardware (Digital)

Company Overview

Renesas is a global semiconductor company providing hardware and software solutions for a range of cutting-edge technologies including self-driving cars, robots, automated factory equipment, and smart home applications. We are a key supplier to the world’s leading manufacturers of the electronics you rely on every day; you may not see our products, but they are all around you.


Renesas is a global, multi-billion dollar, publicly-traded company headquartered in Japan, and has subsidiaries in 20 countries worldwide. Renesas is a dynamic, multi-cultural technology company where employees learn, mentor, innovate and thrive. Renesas is extending our share in fast-growing data economy-related markets such as infrastructure and data center, and strengthening our presence in the industrial/IOT and automotive segments. Our solutions drive products developed by major innovators around the world. Join us and build your future by being part of what’s next in electronics.




Tempe, AZ or Ottawa, ON


Job description


We are looking for a Senior Staff ASIC Digital Design Engineer who will work on the development of state of the art mixed-signal PLL (phase-locked loop) integrated circuits. The Senior Staff ASIC Design Engineer will work on the development of the integrated circuits by doing design specification and RTL coding, front-end implementation and STA, verification, FPGA validation, prototype testing on the bench, etc.


This position will also include being the lead digital engineer on some ICs, i.e., being responsible for the full digital design, including architecture and work/team planning. This will all be done in close collaboration with the analog, digital, implementation and verification engineers, as well the system architects and marketers.


Basic Qualifications


The ideal candidate will have the following attributes:


• Experience with architecting digital designs and writing device-level or sub-system specifications
• Experience with Verilog and/or SystemVerilog for digital design and verification
• Experience in digital design implementation including logical synthesis and DFT insertion with high coverage
• Experience in static timing analysis and creation of place and route constraints
• Experience in formal verification, lint and CDC checking
• Experience in asynchronous clock crossings and synthesis implications of RTL
• Experience in implementing and verifying ECOs on RTL, synthesized, and post route netlists
• Experience with gate-level simulations, causes and implications of timing violations
• Experience in ATPG and ATE support
• Experience with scripting in Tcl, Python, Perl, bash, etc.
• Fast learner with ability to work under minimal supervision
• Strong organization and communication skills


Preferred Skills & Knowledge


• Knowledge of timing and synchronization standards is a strong asset
• Experience with mixed signal circuits is an asset
• SOC design experience is an asset
• Experience with leading a small team is an asset




• Electrical or Computer Engineering degree and 12+ years of practical experience.


Renesas is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment regardless of race, color, religion, sex, national origin, disability, protected veteran status, or any other characteristic protected by law. Renesas is committed to providing accommodations for people with disabilities. If you require an accommodation, we will work with you to meet your needs.#LI-ED1