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Title:  Sr. Staff AMS/Digital Verification Engineer

Company:  Renesas Electronics America Inc.
Country/Region:  US
State:  CA
City:  Milpitas
Department: 
Business Unit:  Automotive Solution Business Unit
Office:  Milpitas
Job Function:  Hardware (Digital)
Job Type:  Permanent
Description: 

Renesas Electronics Americas (REA) is a dynamic, multi-cultural tech company where employees can learn, mentor and thrive. REA brings together the strong financial foundation of a multi-billion dollar global operation and the flexibility and velocity of a smaller organization. We are developing technologies for the latest advances in mobile computing, secured connected devices, autonomous driving, smart homes and factories and more. Our solutions are at the heart of products developed by the major innovators around the world. Join us and be part of what’s next in electronics.

 

Position Details:

A Sr. Staff Level AMS/Digital Verification Engineer to join the Automotive Power IC (PMIC) Design Group at Renesas Milpitas, California Design Center. This Engineer will lead the verification for the cutting edge power solutions for Automotive Application Processors (System on Chip, SOCs), which will provide challenging learning opportunities.

 

Responsibilities:

  • Lead the verification efforts for a derivative or brand new PMIC developments.
  • Extract verification objectives from specification and review them with the team.
  • Define the verification strategy/plan and execute it.
  • Develop test benches and verification components.
  • Define and implement test scenarios and test cases at IC and system level.
  • Develop behavioral models for analog IC components.
  • Setup and run regression tests and coverage analysis.
  • Develop production test pattern and support during initial setup on ATE.
  • Work in a team environment with low levels of supervision and participate in design reviews.

 

Requirements:

  • Degree in Electrical or Computer Engineering.
  • Bachelor's with 10+ years or Master's with 8+ years of relevant experience.
  • Multiple years’ of experience in digital functional verification.
  • Experience with state-of-the-art verification methodologies (UVM/OVM), Assertions/Fault Injection, Coverage Collection and Gate Level Simulations.
  • Experience with developments in hardware descriptive languages: Verilog, System-Verilog, and/or Verilog-AMS code.
  • Experience in setting up and running chip top level AMS simulations.
  • Knowledge of scripting languages, PMIC end-applications, parasitic parameter extraction and functional safety are a plus.
  • Analytical approach to problem solving.
  • Working knowledge of Mixed-Signal Cadence tools (ADE-L, ADE-XL) and simulators (Spectre, AMS, Incisive).
  • Good communication skills.

 

Equal Opportunity Employer: Disability/Veteran


Nearest Major Market: San Jose
Nearest Secondary Market: Palo Alto