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Title:  Principal Digital Verification Engineer

Company:  Renesas Electronics America Inc.
Country/Region:  US
State:  CA
City:  Milpitas
Department: 
Business Unit:  Automotive Solution Business Unit
Office:  Milpitas
Job Function:  Hardware (Digital)
Job Type:  Permanent
Description: 

Renesas is a global semiconductor company providing hardware and software solutions for a range of cutting-edge technologies including self-driving cars, robots, automated factory equipment, and smart home applications. We are a key supplier to the world’s leading manufacturers of the electronics you rely on every day; you may not see our products, but they are all around you.

 

Renesas is a global, multi-billion dollar, publicly-traded company headquartered in Japan, and has subsidiaries in 20 countries worldwide. Renesas is a dynamic, multi-cultural technology company where employees learn, mentor, innovate and thrive. Renesas is extending our share in fast-growing data economy-related markets such as infrastructure and data center and strengthening our presence in the industrial/IOT and automotive segments. Our solutions drive products developed by major innovators around the world. Join us and build your future by being part of what’s next in electronics.

 

Position Details: 

 

A Principal Level Digital Verification Engineer for the Automotive VSP (Video Signal Processing) and BMS (Battery Management systems) Design Group at Renesas Milpitas, California Design Center. This Engineer will lead the verification team for the cutting edge video solutions for Automotive Application Processors (System on Chip, SOCs), which will provide challenging learning opportunities.
 
Responsibilities:
• Lead the verification efforts for derivative or new ASSP developments. 
• Extract verification objectives from specification, review them with the team and build a verification plan.
• Build verification infrastructure by developing test benches and verification components.
• Define and implement test scenarios and test cases at IC and system level using Verilog, SystemVerilog
• Work with Analog designers to develop Verilog and/or AMS behavioral models for analog IP and use them in the verification environment
• Setup and run regression tests, generate coverage metrics and generate targeted test-cases to improve functional and code coverage.
• Work in a team environment with low levels of supervision and participate in design reviews.
 
Requirements:
• Degree in Electrical or Computer Engineering.
• Bachelor's with 15+ years or Master's with 12+ years of relevant experience.
• Expertise with developments in hardware descriptive languages: Verilog, System-Verilog, and Verilog-AMS 
• In-depth expertise with Cadence & Synopsys simulators, verification environment, debugging and waveform tools is a must.
• Proven experience in setting up verification infrastructure, building verification platforms and scripting.
• Experience with state-of-the-art verification methodologies (UVM/OVM), Assertions/Fault Injection, Coverage Collection and Gate Level Simulations is highly desirable.
• Capability to code and debug synthesizable Verilog design is a plus
• Experience with C/C++ Programming is a plus
• Exposure to Mixed-Signal Cadence tools (ADE-L, ADE-XL), simulators (Spectre, AMS, Incisive) and verification management tools (vManager) is a plus.
• Ideal candidate will have an analytical approach to problem solving and should be a team player.
 
Equal opportunity Employer: Disability/ Veteran


Nearest Major Market: San Jose
Nearest Secondary Market: Palo Alto