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Title:  Sr Staff Digital Engineer

Requisition ID:  52501
Department: 
Location: 

Indiranagar, IN

Job Function:  Hardware Engineering

Job description

We are expanding our Physical Design (PD) and Design for Test (DFT) team to help our design teams with the verification and development of successful designs throughout the company. Our team’s goal is to provide strong backend Design-for-Testability (DFT) support and services.

We are looking for a qualified DFT engineer to join the PD and DFT design team. DFT is a multifaceted job that involves test planning, logic design, verification, test patterns generation, chip bring-up and more. As a DFT engineer, you will impact and see the device through its entire lifecycle, from definition stage to mass production. You will work in close collaboration with multiple engineering design groups including chip design, verification, backend, test, reliability and more.

 

Responsibilities

• Responsible for planning and implementing DFT in Renesas designs, verify functionality, and support DFT into Production Test
• Manage the whole DFT design flow from DFT planning, insertion, ATPG, verification to successful production test release
• Communicate with Design, Physical Design and Test Engineers on technical related issues, input requirement and deliverables

• Analyze and suggest design change for Test coverage improvement.

 

Qualifications
8+ years of experience in DFT and semiconductor industry

Solid understanding of DFT techniques: Scan, Memory Bist, Boundary Scan

Knowledge of Mixed Signal DFT Techniques and Methods would be an advantage