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Title:  Sr Mgr, Verification Engineering

Requisition ID:  38638
Department:  RF Communications Department

Indiranagar, IN

Job Function:  Validation Engineer

Job Type: Permanent  - Full Time 

Travel Required: 0% 

Remote Work Available: Yes 


Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of the electronics you rely on every day; you may not see our products, but they are all around you.


Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.

DV Lead

Purpose: The purpose of this job is to lead a team of engineers in the tasks of guaranteeing specification compliance of digital or mixed signal design by means of advanced verification methodologies and concepts. It involves definition, deployment and improvement of state-of-the-art verification methodologies.



  • Lead digital verification of mixed signal ICs or sub-systems.
  • Provide a technical interface between other CMS teams and any local contract DV resources.
  • Develop verification strategy for digital and mixed signal IPs and implement the verification. IP following object-oriented programming principles and methodologies including UVM
  • Verification planning, maintenance, feature extraction, verification tests, coverage and checker development.
  • Develop efficient, reusable state-of-the-art verification environments and testbench structures.
  • Initiate and participate in review meetings with design and verification engineers.
  • Able to debug the RTL for design intent and interface with cross-functional teams and collaboration in all verification related activities.
  • Mentor verification team and provide technical support for verification activities.



  • The ideal candidate has an experience of 8-10 years in advanced verification methodologies, owning the verification of complex digital and mixed signal designs

System Verilog for verification using advanced verification methodologies (preferably UVM 

  • or similar such as Specman-e, OVM, SystemC, etc.)
  • Assertion based verification and Formal verification
  • Expert in constrained random verification and metric driven verification
  • Expert in simulation and regressions tools e.g. Cadence Incisive, vManager, IMC
  • Familiar with either Verilog or VHDL RTL coding and ASIC design methodology
  • Familiar with behavioral modelling of analog blocks
  • Good knowledge of UNIX shell scripting, Perl and TCL scripting
  • Proven experience in writing verification plans and test bench development, simulation and debugging


  • Concise and proactive communication skills within a multi-site and multi-cultural environment
  • Ability to persuade and influence others based on technical facts
  • Ability to interact with customers
  • Ability to successfully work with 3rd party contractors
  • Takes responsibility for solutions and makes them happen, self-motivated
  • Looks for continuous improvement in own and Dialog work practices
  • Good analytical and problem-solving skills