Title:  Principal Electrical Engineer - Design Verification

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of the electronics you rely on every day; you may not see our products, but they are all around you.

Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.

Opportunity for a talented individual for their memory interface products. We are looking for a candidate with a strong background in the verification of complex integrated circuits.  The candidate needs to have skills that are up to date with the latest IC verification tools and flow.  The candidate will work closely with design, applications, and test engineering.   In addition, strong collaboration and communication skills are a must.

Duties/Responsibilities 

·         Develop verification testbench components for chip/module level using SystemVerilog, C & Perl

·         Use high Lehigh-level concepts (Object-oriented, UVM, etc) to develop an extendable environment

·         Define and execute detailed verification plan from spec working with architects, designers, system engineers

·         Incorporate code coverage, functional coverage, assertions, cover groups, etc to achieve 100% verification completeness prior to tape-out

·         Debug tests, run gate-level simulations

·         Develop automated/scripted design flows for the above-mentioned development processes

·         Participate in silicon debug and analysis

·         Support generation of production test vectors

Competencies: Skills, Experience, Knowledge

·         MS in Computer or Electrical Engineering with a minimum of 5+ years of experience in design/verification management of highly complex projects

·         Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required

·         Must be good in building verification environments preferably using the verification subset of high level languages like System Verilog (OVM, UVM)

·         Must be proficient in Verilog (System Verilog preferred).

·         Proficiency in a scripting languages like Python, Perl, Tcl/Tk, Shell is a definite plus.

·         Experience with simulators like ncVerilog (Incisive), VCS, and debug tools like DVE, Simvision, Verdi

·         Good understanding of the latest formal verification techniques, assertions, OOP, etc, and experience with AMS/DMS verification, cosims, gate level Verilog, and RTL synthesis are good to have.

·         Understanding or prior experience with Industry standard protocols like DDR4/DDR5 is a definite plus

·         Good written and oral communication skills. Ability to clearly document plans.

·         Ability to interface with different teams and prioritize work based on project needs.