Title:  Layout Engineer

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of the electronics you rely on every day; you may not see our products, but they are all around you.

Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.

Job Purpose:

Support team in floor planning and layout of mixed signal circuits activities. You will be expected to deliver high quality, high yield layouts in agreed timescales.

Dimensions:

17. Financial data (e.g. sales/revenue budgets).
18. People data (e.g. number of reports managed, 2nd level line manager).
19. Other relevant statistics (e.g. value of contracts managed, payroll costs)

Principle Accountabilies:

• Support floor planning of layouts, in collaboration with designer and lead layout engineer, to ensure cell dimensions, orientation and pin placement are optimized.
• Develop skills using state-of-the-art layout techniques for matching accuracy, parasitic reduction and yield optimization.
• Support routing & verification (DRC, ERC, LVS) of circuit layout.
• Participate in layout reviews and ensure management is well informed of time scale estimates, progress against project plans and any arising issues.
• Work closely in collaboration with colleagues in design and layout to minimize need for rework.
• Develop expertise in deep submicron layout techniques.
• Develop expertise in the required CAD tools (Virtuoso XL / Calibre DRC, LVS & PEX / PVS / R3D)
• Follow methodology guidelines to ensure easy portability of IP across designs.
• Help resolve issues (CAD / PDK / process) alongside colleagues in corporate engineering.
• Take proactive approach to driving own development plan, utilizing team members and internal development opportunities.

Key Performance Measures:

• Deliver first time right layout without the need of significant rework from layout reviews.
• Deliver layouts in the time scales agreed with project manager.
• Deliver layouts free from DRC / ERC / Antenna or LVS issues.
• Able to deliver under tight schedule pressure.
• Demonstrate continuous improvement of technical, non technical sills and use of CAD tools, measured through manager review.
• Demonstrate ability to build effective relationships with relevant stakeholders and be a Team player
• Timely progress reporting and highlighting of risks/issues.

Knowledge, Skills, Experince:

• Typically, 2-5 years’ experience.
• Solid understanding of electronics and semiconductor physics preferably to degree level.
• Developing expertise in analog layout techniques such as floor planning, matching, latch up prevention and verification.
• Skilled use of required IT software (Windows / Unix / Office / Teams)
• Desire for continued learning and development.
• Cross cultural awareness and sensitivity.
• Results-oriented and able to deliver on-time under tight schedules.
• Ability to work both independently and part of a team.
• Flexible to undertake occasional international travel at short notice.
• Excellent command of verbal and written English.
• Ability to propose innovative solutions.
• Concise and precise communication and presentation skills within multisite and multicultural environment.