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Title:  Design Verification Engineer

Requisition ID:  52850

Indiranagar, IN

Job Function:  Engineering



Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of the electronics you rely on every day; you may not see our products, but they are all around you.


Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.




Job Purpose and Dimensions:

The purpose of this job is to help guarantee specification compliancy of the digital design by means of verification methodology and concepts. It supports the definition and enhancement of state-of-the art methodologies serving as clear verification sign-off criteria for tape out.


Principal Accountabilities:

  • Support a technical interface between other CMS teams and any local contract DV resources. 
  • Support verification strategy for digital and mixed signal IPs and implement the verification IP following object-oriented programming principles and methodologies including UVM.
  •  Support Verification planning, maintenance, feature extraction, verification tests, coverage and checker development.
  •  Support the development of efficient, reusable state-of-the-art verification environments and testbench structures.
  •  Attend review meetings with design/verification engineers
  •  Support physical silicon device evaluation where necessary, and develop work-around solutions to overcome device errata
  •  Able to debug the RTL for design intent and interface with cross-functional teams and collaboration in all verification related activities.


Knowledge, Skills and Experience:

  • The ideal candidate has an experience of 2- 5 years in state-of-the art verification methodologies related to the verification of SoCs · Fluent in System Verilog RTL coding and ASIC design methodology · System Verilog for verification using advanced verification methodologies (preferably UVM or similar such as Specman-e, OVM, SystemC, etc.)
  •  Assertion based verification and Formal verification
  •  Fluent in constrained random verification and metric driven verification
  •  Fluent in simulation and regressions tools e.g., Cadence Incisive, vManager, IMC
  •  Familiar with either system Verilog or VHDL RTL coding and ASIC design methodology
  •  Familiar with behavioral modelling of analog blocks would be benficial
  •  Good knowledge of UNIX shell scripting, Perl and TCL scripting
  •  Experience in writing verification plans and test bench development, simulation and debugging
  • General: · Concise and proactive communication skills within a multi-site and multi-cultural environment
  •  Ability to persuade and influence others based on technical facts.
  •  Ability to interact with customers · Ability to successfully work with 3rd party contractors
  •  Takes responsibility for solutions and makes them happen, self-motivated
  •  Looks for continuous improvement in own and Renesas work practices
  •  Good analytical and problem-solving skills



Degree in electrical engineering, electronics, computer engineering, computer science, or equivalent