Title:  Senior Engineer

Physical Design/ DFT

• Physical Design: physical synthesis, place & route, timing closure and timing/physical verification for IP, CPU and Chip design.
• DFT: Design for testability (Memory/Logic BIST, SCAN, Boundary Scan) insertion, verification and test pattern generation for IP, CPU and Chip design
• Join training program to master EDA tools before actual job
• Initially mentored by a senior engineer in actual job

Job requirement

• Fresh university graduates with major in Electronics, Telecommunications, Mechatronics, Automation, Computer Science, Computer Engineering, Information Technology, Mathematics – Computer Science, Physics – Electronics, and Physics – Computer Science
• Good at English in both writing and speaking skills, distinguished competence, consistent in pursuing of excellence, professional behavior, and good relationships with others and society.
• Have strong passion in technical field, especially in chip design.
• Have logical thinking and explanation; be serious and mature in working attitude
• Long term working commitment (at least two years after completion of the training program) with company is a MUST
• #LI-MT1