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Title:  Staff Test Engineer

Department: 
Location: 

San Jose, US

Job Function:  N/A

Renesas is a global semiconductor company providing hardware and software solutions for a range of cutting-edge technologies including self-driving cars, robots, automated factory equipment, and smart home applications. We are a key supplier to the world’s leading manufacturers of the electronics you rely on every day; you may not see our products, but they are all around you.

 

Renesas is a global, multi-billion dollar, publicly-traded company headquartered in Japan, and has subsidiaries in 20 countries worldwide. Renesas is a dynamic, multi-cultural technology company where employees learn, mentor, innovate and thrive. Renesas is extending our share in fast-growing data economy-related markets such as infrastructure and data center, and strengthening our presence in the industrial/IOT and automotive segments. Our solutions drive products developed by major innovators around the world. Join us and build your future by being part of what’s next in electronics.

 

Minimum Requirements
• Bachelor’s degree in electrical/computer engineering or computer science. 
• 6~8 years of experience test H/W and test program development.
• Strong test development and debug skills on Advantest – PS1600. Experience on Teradyne MicroFlex is a plus.
• Hands-on experience on ATE test development for analog and mixed signal devices. Proficient with ATE analog instruments, strong debug/troubleshooting experience
• Strong experience in vectors generation and conversion. Familiar with vector generation tools such as VTRAN/Velocity, and ability to write vector generation tools.
• Strong experience in programming in such as C/C++, Perl, python, etc.
 
Preferred Requirements
• Familiar with high speed ASIC/SOC devices
• Experience on analog ATE test instruments such as AVI/FVI, and programming/debug skills with C++ & SmartRDI
• Master’s degree in electrical/computer engineering or computer science
• Experience in ATE characterization
• Familiar with trimming and MTP/OTP for deep sub-micron devices in production test
• Experience with memory test algorithms
• Experience with serial interfaces such as I2C, JTAG, and SPI

 

Education
BS EE, MS EE preferred

 

Equal Opportunity Employer: Disability/Veteran

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Nearest Major Market: San Jose
Nearest Secondary Market: Palo Alto