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Title:  Sr Staff Mixed Signal Verification Engineer

Company:  Renesas Electronics America Inc.
Country/Region:  US
State:  TX
City:  Austin
Department: 
Business Unit:  IoT and Infrastructure Business Unit
Office:  Austin
Job Function:  Hardware (Digital)
Job Type:  Permanent
Description: 

Renesas Electronics Americas (REA) brings together the strong financial foundation of a multi-billion dollar global operation and the flexibility and velocity of a smaller organization. A result of the combination of Renesas and Intersil, REA has a deep portfolio of technology, a strong customer base and big ambitions to grab more market share on a global stage. Our engineers, marketers, sales and support teams are all unified in our goal to create an environment where creativity thrives, where results are rewarded and where diversity is valued. REA is developing technologies for the latest advances in mobile computing, secured connected devices, autonomous driving, smart homes and factories and more. Our solutions are at the heart of products developed by the major innovators around the world. 

 

Renesas Electronics, the number one global supplier of microcontrollers and a leader in semiconductors, delivers trusted embedded design innovation that enables billions of connected, intelligent devices to enhance the way people work and live - securely and safely.

 

REA is seeking a Mixed Signal Verification Engineer for our Infrastructure Power team in Austin, TX.  Reporting to the Design Engineering Manager, you will have responsibility for the design and verification of power management IC’s that supply power to the world’s largest and most advanced computing platforms. 

 

Responsibilities:

  • Own mixed-mode simulation environment and methods for full custom ASICs for power conversion applications 
  • Develop behavioral models using SystemVerilog real number modeling (sv-rnm)
  • Develop test plans, test benches, and verification methodologies 
  • Create and verify SystemVerilog models from analog schematics, specifications
  • Collaborate with UVM verification engineers to ensure all verification components are used for AMS-UVM flow
  • Develop directed/constrained-random test generation
  • Own AMS regression flow and AMS verification test suite 

 

Required Skills:

  • BSEE with 12-15 years relevant experience,, MSEE & 10, or PhD & 7 
  • Solid understanding of analog circuits (amps, comparators, references, biased) and mixed-signal subsystems (ADC, DAC, PLL, …) 
  • Expertise with Cadence design tools 
  • Solid understanding of RTL
  • Debugging with transistor level schematics
  • Deep understanding of real, wreal and development of custom data structures
  • Excellent communication skills


Required Experience:

  • Development of commercially successful IC’s
  • Track record of first-time silicon success
  • Proven ability to set and meet development milestones


Preferred Skills and Experience:

  • Feedback control systems
  • DC/DC conversion
  • Post silicon validation
  • Flow automation scripting
  • Knowledge of Assertions
  • Verilog-AMS
  • Coverage development
  • Use of tracking systems for development milestones, tasks and bug resolution
     

Equal Opportunity Employer: Disability/Veteran